Trench-gated MOSFETs are a class of MOSFETs in which the gate is positioned in a trench that is formed at the surface and extends into the silicon. The gate is formed in lattice-like geometric pattern which defines individual cells of the MOSFET, the pattern normally taking the form of closed polygons (squares, hexagons, etc.) or a series of interdigitated stripes or rectangles. The current flows in vertical channels which are formed adjacent to the sides of the trenches. The trenches are filled with a conductive gate material, typically doped polysilicon, which is insulated from the silicon by a dielectric layer normally consisting of silicon dioxide.
Two critical characteristics of a power MOSFET are its breakdown voltage, i.e., the voltage at which it begins to conduct current when in an off condition, and its on-resistance, i.e., its resistance to current flow when in an on condition. The on-resistance of a MOSFET generally varies directly with its cell density, since when there are more cells per unit area there is also a greater total "gate width" (around the perimeter of each cell) for the current to pass through. The breakdown voltage of a MOSFET depends primarily on the doping concentrations and locations of the source, body and drain regions in each MOSFET cell.
The MOSFET is typically formed in a lightly-doped epitaxial layer of silicon which is grown on a heavily-doped silicon substrate. The gate trenches normally extend into the epitaxial layer and are frequently rectangular, with flat bottoms bounded by corners. This configuration creates a problem in that, when the MOSFET is turned off, the electric field reaches a maximum near the corners of the gate trenches. This can lead to avalanche breakdown and impact ionization near the surface of the gate oxide, with the consequent generation of carriers. If the carriers are generated within a mean free path of the interface between the silicon and the gate oxide, they may have sufficient energy to pass through the interface and become injected into the gate oxide layer. Carriers that are able to surmount the silicon/silicon dioxide energy barrier are often referred to as "hot carriers." Hot carrier injection can ultimately damage the gate oxide layer, causing changes in threshold voltage, transconductance or on-resistance, and thereby impair or destroy the MOSFET.
U.S. Pat. No. 5,072,266 teaches a technique of suppressing voltage breakdown near the gate by the formation, in the MOSFET cell, of a deep central body diffusion that extends below the bottom of the trenches. This deep central diffusion shapes the electric field in such a way that breakdown occurs in the bulk silicon away from the gate, in a location which prevents hot carriers from reaching the gate oxide layer. A cross-sectional view of a MOSFET in accordance with U.S. Pat. No. 5,072,266 is shown in FIG. 1, which illustrates a MOSFET cell 10 containing a trenched gate 11, an N+ source region 12, an N+ substrate (drain) 13, an N-epitaxial layer 14, and a deep central P+ diffusion 15. Note that the lowest point of P+ diffusion 15 is below the bottom of gate 11.
The doping of deep P+ diffusion 15 is greater than the doping of P-body 16 in the region of the channel, designated by the dashed line and reference numeral 17. As a result, the distance Y.sub.S between the gate trenches must be maintained at or above a minimum value. Otherwise, the deep P+ dopant will diffuse into the channel 17 and raise the threshold voltage V.sub.tn of the device. The value of Y.sub.S, along with the thickness of the gate, defines the cell density and helps to determine the on-resistance of the MOSFET.
Moreover, the deep P+ diffusion limits the spreading of the current in the N-epitaxial region 14. FIGS. 15A and 15B show simulations of the current flow lines in a conventional MOSFET having a flat bottomed P-body region and a MOSFET having a deep P+ diffusion, respectively. The current lines in FIG. 15B are limited to a spreading angle (an analytical approximation used to describe the epitaxial current uniformity) of about 45 to 47 degrees (measured at the 95% flow lines), resulting in sub-optimum utilization of the N-epitaxial region and a higher specific on-resistance than in the device portrayed in FIG. 15A. The large current-spreading angle of the conventional device, which ranges from 73 to 78 degrees, achieves uniform conduction at a significantly shallower depth as estimated by the expression x=(Y.sub.CELL -Y.sub.G)2tan.theta., where .theta. is the current spreading angle, Y.sub.CELL is the total width of the MOSFET cell, and Y.sub.G is the distance between the gate trenches. This relationship is pictured in FIG. 16. It has been found that the presence of the deep P+ region increases the depth at which uniform conduction is achieved in the N-epitaxial region from 0.5 microns to 1.6 microns.
To fabricate an extremely low voltage, low on-resistance power MOSFET, the dimensions of the device are generally scaled down. In particular, the cell density is increased and the epitaxial layer is made thinner, even to the point that the gate trenches may extend into the heavily-doped substrate. Such a MOSFET is illustrated as MOSFET 20 in FIG. 2A.
This creates an entirely new set of design criteria. Referring to FIG. 2A, since the corners 21C of the gate trenches 21 are surrounded by the N+ substrate 13, the electric field at these locations drops entirely across the gate oxide layer. While the formation of hot carriers in the silicon may be lower, the high electric field on the gate oxide layer may still lead to device degradation or damage. In one condition, when the gate is biased at essentially the same potential as the source and body (i.e., the device is turned off), a serious concern is that the gate oxide layer at the bottom of the trenches must support the entire voltage across the device. Compared to the embodiment of FIG. 1, there is no epitaxial layer to absorb a portion of this voltage difference.
An equivalent circuit for MOSFET 20 is shown in FIG. 2B. Diode D.sub.DB represents the PN junction between N-epitaxial layer 14 and P-body region 22, and capacitor C.sub.GD represents the capacitor across the gate oxide layer 21A.